Our customer wants to test pure digital ASIC (Application-Specific Integrated Circuit). To test their IC, they need to stimulate the IC with a several specific bit-patterns. To verify that the ASIC is functionally right, they need to collect data from the IC when each set of patterns is applied.

The stimulus must be 'real-time', each set of stimulus is composed of input vectors, each vector being applied onto the ASIC inputs during an equal time defined as the 'pattern frequency'. The customer has defined a pattern frequency of 50 MHz - in other words, a new stimulus vector is applied onto the IC inputs each 20 nanoseconds.

The customer wants to use a pattern generator to generate stimulus to test their ASIC and simultaneously capture the response from the IC from some of its outputs. The input stimulus exists from ASCII files extracted from testbenches used in simulation. It is formed of a table of 1's and 0's. Each columun corresponds to the stimulus to be applied to one single input pin of the ASIC. Each line in the table represents the set of stimuli to be applied at the pattern frequency (so each 20 ns) onto the IC inputs.

The customer has got the following concerns:

1. They want to be able to apply stimuli using a 2.5V LVCMOS standard
2. They want to find a solution that they are able to scale with time.

In their first test setup, they only need to stimulate 16 inputs and wanted to use a bench-top logic analyzer to record the chip's outputs. They wanted to have a solution that could be scaled in time to be able to stimulate more inputs and also to record the outputs from the same control PC.

Byte Paradigm's solution

As pattern generator, Byte Paradigm recommended the GP-24100 in ADWG mode of operation.
This device provides  a 16 bits wide pattern generator with 8 MByte pattern memory and runs up to 100 MHz. The customer liked to go for a 100 MHz device because they knew they would increase the pattern frequency in the future.
GP-24100 also provides an external voltage connector for the I/Os - so the user can provide his own external voltage of 2.5V instead of the standard 3.3V provided by the device.

GP-24100 supports many input formats from binary to ASCII file and also features an advanced C/C++ interface (through DLL function call) which allowed the customer to easily reuse their existing set of tabular input patterns.

For the first application (16 bits stimulus generation at 50 MHz), the GP-24100 was a good fit.

The GP-24100 also provides a logic analyzer mode of operation, which can be used to record the outputs of a digital ASIC.

Initially, there was a limitation with GP-24100 device - the 8PI Control Panel software used to control it only allowed one device to be connected on the same PC. So, this prevented from using a PC and a second device in logic analyzer mode to simultaneously record the ASIC outputs. Similarly, this limitation prevented from using multiple devics in parallel to extend the input pattern and output sample width (limited to 16 bits on each device).

Byte Paradigm has improved 8PI Control Panel software to remove this limitation. Multi-device support is available from version 2.00 of 8PI Control Panel. Byte Paradigm provided an intitial beta version of the new software to the customer for application deployment. The customer is currently developing a new test setup with multiple GP Series devices as source stimulus generators (using the digital pattern generator application) and a GP series device in logic analyzer to sample and observe the IC's behaviour, implementing a complete stimulus-and-response test setup type.

Recommended product

GP Series devices with 8PI Control Panel version 2.00: digital pattern generator (ADWG mode) is used to apply the input stimulus while the analyzer (logic analyzer) mode of operation is used to record the IC's outputs. Multiple devices can be controlled from the same PC (8PI Control Panel version 2.xx).