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Whatever the protocol that your intend to use, the SPI Adapter that you choose will have to generate the reference clock signal to the slave(s) connected on the bus.

SPI protocol and its variants do not define anything regarding the clock frequency. As a consequence, you'll have to check the data sheet of the slaves that you would like to access with the adapter and define the maximum frequency that you need on SCLK.

What is the range of frequencies that can be achieved with Byte Paradigm's devices?

See the table below.
'Internal clock source' supposes that the SPI Adapter device uses its own internal clock and a clock frequency divider to generate the clock signal on SCLK.
'External clock source' supposes that an externally generated reference clock is supplied to the SPI Adapter onto a dedicated input pin. The frequency of this signal is fext. It must be a continuously toggling clock signal.

When using an 'internal clock source', the SPI Adapter will be able to generate a clock signal in a given frequency range by steps. These steps depend on the structure of the internal clock frequency divider.

Device	Conditions	min	max
	Clock source = Internal	98 kHz	100 MHz
	Clock source = External	fext / 1024	100 MHz
	Clock source = Internal	fext / 2^16	50 MHz
	Clock source = External	763 Hz	50 MHz

1) SPI Storm can be used to run below 98 kHz if a data line is used to generate the clock signal and if the protocol is defined as a custom protocol with data repetition (overclocking on all signals).

2) Output SCLK signal frequency is defined by the formula: fSCLK = fmax / 2^(ClockDiv), where:
- fSCLK is the output SCLK signal frequency;
- fmax is the reference clock: when the internal clock source is used, this is equal to 100 MHz for SPI Storm and 50 MHz for SPI Xpress; when the external clock source is used, this is the frequency of the external clock signal.
- ClockDiv is the dividing factor of the internal clock divider.

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